Programmable logic has increasingly become a valued resource for system designers. Programmable logic can allow for a custom logic design to be implemented without the initial cost, delay and complexity of designing and fabricating an application specific integrated circuit (ASIC).
Currently, there are many variations of programmable logic, including simple programmable logic devices (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs). Such devices typically include programmable logic circuits that operate in conjunction with corresponding memory circuits. The particular function of a logic circuit can be determined according to data stored in a corresponding memory circuit. Some programmable logic arrangements can include switching circuits (also called programmable interconnects) that can enable and/or disable switching paths according to data stored in a memory circuit. A memory circuit is typically a nonvolatile memory circuit, such as a programmable read-only-memory (PROM), an electrically programmable ROM (EPROM), and/or electrically erasable and programmable ROM (EEPROM), including “flash” EEPROMs.
A nonvolatile memory circuit can be formed on a different integrated circuit than programmable logic. That is, a programmable logic circuit die can receive configuration information from an associated nonvolatile memory circuit that may be on the same die or a separate die.
In addition to the above basic structure, programmable logic arrangements may have alternate structures. For example, while a system may include a separate programmable logic device and an EEPROM memory circuit, some processes may be capable of forming nonvolatile devices and conventional volatile devices on the same integrated circuit. In such a case, the nonvolatile memory circuit is “on-chip” (or integrated) with a volatile programmable logic circuit.
To configure programmable logic, a memory circuit within the device can be programmed with data values that give the desired functionality. In some arrangements, data can be loaded in a compressed form. The programmable logic may then include a decompression algorithm for decompressing an incoming data bit stream as it is stored within a memory circuit.
Like other integrated circuit devices, the manufacture of programmable logic can include a “front-end” and a “back-end.” The front end of programmable logic manufacturing may include the fabrication of devices on a wafer. The back-end may include slicing wafers into dice, packaging the dice, and testing the resulting packages. With the increasing complexity of programmable devices, testing can become an important step in a manufacturing process.
Back-end testing may include a range of possible tests. For example, at one end of the spectrum, such tests can be basic, checking for opens and shorts in the logic circuits of a programmable logic device. At the other end of the spectrum, such tests can check the particular operation of the logic circuits, including operational speed. Such test can allow non-failing devices to be categorized (binned) according their operating characteristics (e.g., speed).
In some arrangements, a tester can be loaded with a test program that exercises various functions of a programmable logic device. Such an approach can be time consuming as a tester must apply various input signals and wait for the resulting input signals. In addition, between different devices and/or different tests, test program data may have to be loaded into the tester.
One way to address the complexity, cost and delay in testing programmable logic has been to include self-test circuitry on the device itself. Such approaches have been referred to as “built-in-self-test” (BIST). Programmable logic with BIST capabilities can reduce test times. Instead of having a tester exercise various tests, such tests can be run on the chip itself, which is typically much faster. Programmable logic with BIST capabilities can further reduce the burden on a tester. Instead of having a tester sequence through various functions, a tester may only have to read a pass or fail indication. Consequently, simpler, less expensive testers can be used.
A drawback to conventional programmable logic BIST has been the resulting area that BIST circuits require. Such additional area can increase the overall size the resulting devices, increasing manufacturing costs. In particularly, a typical BIST approach can include numerous multiplexer circuits formed in the logic circuits that provide certain signal paths in a “normal” mode and different signal paths in a test mode. In addition, BIST circuits may include additional logic gates for logically combining various output signals to generate a test result. In addition to increasing overall area, the incorporation of such “hard” logic circuits into the existing logic circuits can add complexity to the design, complicating circuit layout and routing. Added complexity arises out of the need to include such hard logic BIST circuits without adversely affecting normal mode signal propagation times.
To better understand the operation of the various embodiments of the present invention, the operation of a conventional programmable logic device with BIST capabilities will now be described.
Referring now to FIG. 8A, a programmable logic assembly 800 is shown that includes a nonvolatile memory 802, a volatile programmable logic device (PLD) 804, and a test port 806. As noted above, a conventional volatile PLD 804 can include area dedicated to normal logic circuits 804-0 and area dedicated to BIST circuits 804-1. Of course, the areas 804-0 and 804-1 are conceptual representations, as BIST circuits are typically intermixed within the normal logic circuits. Areas 804-0 and 804-1 are provided to illustrate how conventional BIST approaches can result in larger integrated circuit areas.
FIG. 8A shows the initiation of a self-test operation for a programmable logic device 800. A volatile PLD 804 can receive a self-test command. Such a command could be initiated in a variety of ways, including but not limited to, a particular combination of input values, an “overvoltage” applied to one or more particular pins, and/or upon power-up of the device. A self-test command may be issued by a number of sources. As but of few of the many possible examples, a self-test mode may be initiated by a tester machine, a user, and/or by a system in which a PLD is a part.
FIG. 8B shows a self-test operation result. A volatile PLD 804 can execute a self-test operation with internal BIST hard logic and generate one or more self-test results. In the particular example of FIG. 8B, a self-test result may be output by way of test port 806. A self-test result could be provided to a tester machine, to a user, or to a system, as but a few examples.
In the event a self-test result indicates that a PLD 804 is functioning properly, the programmable logic device 804 may be configured as desired by a user. FIG. 8C shows a conventional programming operation. Configuration data may be entered that can establish a user-defined functionality for the PLD 804. In particular, configuration data may be entered by a user through test port 806 and programmed into a nonvolatile memory 802. In one particular arrangement, configuration data can be entered in a compressed data stream. A PLD 804 may include hardware for decompressing such a data stream.
While a conventional assembly 800 such as that shown in FIGS. 8A to 8C can provide BIST functionality, it comes at the cost of increased circuit area on a PLD 804.
In light of the above discussion, if would desirable to arrive at some way of implementing self-test on a programmable logic device that does not result in undue increases in the area dedicated to built-in-self-test circuits.
It would be desirable to arrive at some way of implementing self-test on a programmable logic device that can be more economical than conventional approaches.
It would also be desirable to arrive at a way of testing programmable logic devices that does not necessarily require complex tester machines and/or programs.